[e2e] Re: [e2e], [Tsvwg] Really End-to-end or CRC vs everything else?
jonathan at DSG.Stanford.EDU
Fri Jun 8 10:46:14 PDT 2001
In message <200106081723.f58HN3t24578 at codex.cis.upenn.edu>,
Michael B Greenwald writes:
> Thu, 7 Jun 2001 17:41:36 -0700
> "Douglas Otis" <dotis at sanlight.net>
> The stuck bit tests for the more elaborate two Fletcher-16 sums indicated
> that errors were undetected 1.3% of the time using disk files as test cases
> if a stuck memory bus bit affected only half of the packet.
>Could you send me a pointer to the paper that reports these measurements
>and explains your experiments? 1.3% sounds high --- especially if you are
>using a 32bit Fletcher checksum (a 16bit sum and a 16bit sum of products).
>I'd like to understand this result.
Doug posted a URL to his simulation code to tsvwg. (Be sure to get
the moe recent version with bug-fixes for the checksum computaiton).
Doug's error model is to simulate stuck-bit errors in each of the 32
positions in a 32-bit word: the `stuck' bits forces all bit positions
in that packet to the `stuck' value. (the simulation does
stuck-at-one and stuck-at-zero).
Doug was using mod-2^n checksums ( two 16-bit counters computed
mod-65536). IEN-45 has a discussion explaining why a mod 2^n sum
gives weaker coverage to the high-order bit than does a mod ((2^n)-1)
sum. It would be interesting to look at how often it's the high-order
bit for which stuck-bit errors go undetected.
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