[e2e] Re: [Tsvwg] Really End-to-end or CRC vs everything else ?

julian_satran at il.ibm.com julian_satran at il.ibm.com
Sun Jun 10 05:18:25 PDT 2001

It is also hard for an "outsider" ("out-of-the-Central-Electronic-Complex")
to say what end-to-end is.
If end-to-end is "memory-to-memory" then computing the checksum with a CPU
or with an outboard
engine differ only in the buses they take the data through and I am not
sure that you will want to trust more or less the memory-to-CPU bus than
the memory-to-adapters bus.


Vernon Schryver <vjs at calcite.rhyolite.com> on 09-06-2001 02:43:18

Please respond to Vernon Schryver <vjs at calcite.rhyolite.com>

To:   end2end-interest at postel.org
Subject:  Re: [e2e] Re: [Tsvwg] Really End-to-end or CRC vs everything else

> From: Jonathan Stone <jonathan at dsg.stanford.edu>

>                       ...  It's that computational-cost knee which is
> of concern: pick a function any more costly and it'll be put into
> outboard hardware, with enough of a benchmark win for people to turn
> on the outboard checksums; thus destroying the end-to-end property of
> the error check.

Assuming we are thinking about the same meanings for "outboard," and as
one of those nasty, cheating people who have put checksum stuff outboard
in commercial products, I disagree.  There is no computational-cost knee,
although there might be a computational-cost/performance slope.  If you
really care about speed, then even the TCP checksum is worth doing
outboard, even if your host CPU's have lots of 64-bit registers and
multiple pipelines so that you can sum lots of bits in parallel and so
can do sum many data bytes per CPU cycle.

Think about how you would build the fastest commercial practical NFS
(Network File System) server.  Such a box is related to a ttcp or
netperf benchmark number generator that generates large number.  In
such boxes, the host CPU never touches the data, because you cannot
afford the enormous number of cycles that come from a cache miss for
any plausible cache width.  In the NFS case, the box might make data
pause in main memory on its way between the wires and the media, but
it won't waste time getting it into any of its 3 or more levels of
CPU data cache just so the CPU can fondle it.  The host CPU will deal
with the headers, but the data will be checksummed either entirely
outboard or as it flies through the DMA machinery.

Vernon Schryver    vjs at rhyolite.com

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